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Arm Cortex-A9 for Zynq System Design Online
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
This course covers both the system and software aspects of designing with an Arm® Cortex®-A9 MPCore based device, highlighting the core architecture details and the AMD Zynq™ programmable SoC implementation choices.
Topics include the Arm exceptions model, details of the available caching schemes and coherency management, memory management and the Arm memory model. Additionally the sections on the v7 architecture instruction set and steps involved in initializing an MPCore system deliver the essential knowledge required for programming and debugging a Cortex-A9 MPCore processor.
The learning is reinforced with unique lab exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
The format of Live ONLINE training from Doulos is focused on delivery of a single 4 hour intensive session per day. This includes live tuition and class interaction with the Doulos subject matter expert during the full scope of each session.
Labs are usually incorporated within the 4 hour sessions with the Doulos lab platform providing individual (private) tutor support at all times for each delegate. On occasion, labs may require time outside of the 4 hour session to complete. Additional lab material is available in some subjects for individuals to reinforce their understanding of the course content.
Engineers who wish to learn about other features and benefits of the AMD Zynq programmable SoC (aside from details of the Arm Cortex-A9 processing system) may wish to attend Zynq SoC System Architecture Online, which covers the architecture of the processing system (PS) and the integration of programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize Zynq.
Delegates should have some knowledge of embedded systems, and a basic understanding of embedded programming in C and assembler.
Knowledge of earlier Arm architectures is an advantage but not necessarily required.
The source training materials include novel content (presentation and labs) developed by Doulos supplementing approved training materials provided under license from Arm for Arm Cortex-A9 MPCore software design.
Introduction to Zynq
Introduction to the Arm v7 instruction set architecture
Hands-on Lab session
Caches
Exception Handlers for Arm application processors
Hands-on Lab session
Memory Management
Using the NEON co-processor
Writing C for Arm
Synchronization Support
Embedded software development
Software Engineer's Guide to Zynq
MPCore Logic
TrustZone Overview
The learning is reinforced with unique Lab Exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on the default development tool-set offered by AMD as well as a remote debug session based on a combination of GDB and the Zynq QEMU platform used for fast prototyping.
Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/CGDB and QEMU).
Complete an enquiry form and a Doulos representative will get back to you.
Enquiry FormPrice on request
