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Arm Cortex-A9 for Zynq System Design
This course is available Live Online worldwide: View the Live Online full course description »
Overview
This course covers both the system and software aspects of designing with an Arm® Cortex®-A9 MPCore based device, highlighting the core architecture details and the AMD Zynq™ implementation choices. Topics include the Arm exceptions' model, details of the available caching schemes and coherency management, memory management and the Arm memory model, as well as the AMBA AXI bus protocol. Additionally the Arm assembly section delivers the essential knowledge required for programming and debugging an Arm v7 based application processor.
Hands-on Labs
The learning is reinforced with unique lab exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
Associated learning
Engineers who wish to learn about other features and benefits of the AMD Zynq programmable SoC (aside from details of the Arm Cortex-A9 processing system) may wish to attend Zynq SoC System Architecture, which covers the architecture of the processing system (PS) and the integration of programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize Zynq.
(Zynq SoC System Architecture covers the Cortex-A9 architecture in approximately 1 hour as opposed to 3 days.)
Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.
C Programming for Embedded Systems training is also available from Doulos.
A carefully crafted combination of content from Arm, AMD and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes:
Introduction to Zynq
Caches and Tightly Coupled Memories
Introduction to Arm assembler programming (including Labs - see below)
Using the NEON co-processor
Exception Handlers for Arm application processors
Memory Management
Synchronization Support
Embedded software development
Software Engineer's Guide to Zynq
MPCore Logic
The AMBA AXI bus protocol
Appendix:
Introduction to TrustZone
Compiler Hints and Tips
Linker and Libraries
The learning is reinforced with unique Lab Exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on the default development tool-set offered by AMD as well as a remote debug session based on a combination of GDB and the Zynq QEMU platform used for fast prototyping.
Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/CGDB and QEMU).
Complete an enquiry form and a Doulos representative will get back to you.
Enquiry FormPrice on request
