Fast-track Verilog for VHDL Users is an intensive 2-day conversion-training course teaching the application of the Verilog® Hardware Description Language for programmable logic and ASIC design. It is not suitable for engineers who haven’t already attended the Comprehensive VHDL course or are not well practised in VHDL based design.
By emphasising the similarities and highlighting the differences between the VHDL and Verilog languages and the associated design flows, this course fast-tracks delegates through the Verilog learning curve. It is designed to enable VHDL based engineers to be Verilog-ready for transition to SystemVerilog application. (Check out scheduling and packaging options with SystemVerilog for Designers, Comprehensive SystemVerilog and Modular SystemVerilog.)
- require this training prior to attending a scheduled Comprehensive SystemVerilog course, or
- have an onsite team based training requirement (for which the course content, scope and duration can be customised to the best fit your specific context),
The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools. A number of supplementary topics are also available, including a preparatory overview of SystemVerilog.
Workshops comprise approximately 50% of class time and are based around carefully designed exercises to reinforce and challenge the extent of learning. Because Doulos is an independent company, our clients can choose the design tools used during the workshops.