PCIe Protocol Overview

FPGA designers, logic designers and anyone who needs an in-depth knowledge of the PCIe protocol

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After completing this comprehensive training, you will know how to:

• Interpret various transactions occurring on the link
• Describe the layered architecture and the tasks and packet types each is responsible for
• Properly estimate maximum performance of a link
• Illustrate how errors can be communicated within the system
• Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow control credits

Lab 1: Packet Decoding – This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.