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This course is available Live Online worldwide: View the Live Online full course description »
In-person training schedule under review for 2022. Please contact us to discuss your requirements for in-person individual and team training.
Essential Digital Design Techniques is a fast-track, application orientated course designed to bridge the gap between text book theory and real world digital design practice.
It significantly accelerates the on-the-job learning curve for engineers new to digital design, or those needing to refine their design skills before project involvement. With a strong emphasis on practical design and hands-on workshops, this course has been specifically developed to capture design techniques usually learned over months, in an intensive 2-day format.
Essential Digital Design Techniques provides the ideal first stage in full scale project training for graduate design engineers, or engineers moving into digital design from other disciplines (including software or analog design). As such, it is the natural precursor to the Doulos Comprehensive VHDL and Comprehensive Verilog courses, which prepare engineers for HDL application within FPGA or ASIC design projects.
Delegates require no prior involvement in digital design projects or HDL knowledge, but should be familiar with the basic principles of digital electronics. Some background refresher reading can be suggested prior to the course if required (contact Doulos for details, or to discuss course suitability).
PLEASE NOTE: this course does not teach, or require knowledge in a specific Hardware Description Language.
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Course Fees include:
Designing with programmable logic and ASICs • Synchronous design techniques • Using HDLs
Representing bits and three-states • Unsigned and signed (two's complement) numbers • Static and dynamic definition of combinational logic • Logic minimisation • Avoiding asynchronous sequential logic
Principles • Using D-type flip-flops • Characterisation - timing constraints • Timing violations and metastability issues • Timing performance of synchronous systems • Static timing analysis • Other flip-flop types
First and second generation HDLs • VHDL and Verilog • Design process using HDLs
Survey of programmable logic devices •: Selecting an appropriate device • Importance of the internal structure • I/O pin standards • Pull-ups; open collector; tristates and bi-directional tristate bubble-up • Pin assignment • JTAG boundary scan
Encoders and decoders • Priority encoders • Multiplexers • Tristates used as Muxes • Parity generator • Shift Registers • Johnson (ring) "counters" • Linear Feedback Shift Registers
Half and full adders • Large adders •: Carry lookahead adder • Pipelining • Synthesis of adders • Counters • Wide counters • Binary to BCD conversion • Serial arithmetic • Importance of synchronous design
Definition • Graphical entry and symbolism • Moore and Mealy structures • Implementation • State encoding and optimisation • Using HDLs to design FSMs • Using memories • Memory types
ASIC types and technologies • ASIC economics • Design for test • Design process for ASICs
|3 Apr 2023||Paris, FR||Enquire|
|17 Apr 2023||Ankara, TR||Enquire|
|12 Jun 2023||Ankara, TR||Enquire|
|19 Jun 2023||Heesch, NL||Enquire|
|7 Aug 2023||Ankara, TR||Enquire|
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