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Comprehensive SystemC is a 5-day training class introducing SystemCTM, a C++ class library for system-level modelling. SystemC is typically used to model systems that have both hardware and software content at the transaction level of abstraction.
The syllabus covers the SystemC core language and its application to transaction-level modelling. The class complies with IEEE 1666-2005 and the SystemC 2.2 class library.
Comprising 2 modules, engineers can attend either the full 5-day class or just the Fundamentals of SystemC module. Attendance of both modules is recommended unless attendees already have a good background in the use of C++.
Fundamentals of SystemC includes an introduction to the SystemC TLM-2.0 standard. TLM-2.0 is taught in more detail in a separate 3-day follow-on class SystemC Modeling using TLM-2.0.
The workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. Delegates can use the tools and platform of their choice in all exercises and workshops.
Doulos has a world-wide lead in independent SystemC know-how having been active in SystemC-based methods since 2000. We have delivered SystemC training and support to engineers in more than 500 companies world-wide - including direct involvement with methodology and tool developers in such companies as ARM, Cadence, CoWare, Mentor Graphics and Synopsys.
Essential C++ for SystemC
Delegates need basic knowledge of the C programming language, in particular familiarity with C functions, variables, data types, operators, and statements. This module is suitable for people with no previous knowledge of C++, as a refresher for those with limited knowledge of C++, or for hardware engineers who are familiar with VHDL or Verilog®.
Fundamentals of SystemC
A working knowledge of C++ and of object-oriented programming concepts is essential and basic knowledge of hardware design is recommended. Prior attendance of the Doulos Essential C++ class (or equivalent) is required. Delegates with C++ experience should check their knowledge against the SystemC C++ Pre-requisites available from Doulos before attending. The course is suitable for electronic hardware, software or systems engineers, but in order to gain maximum benefit from this course, delegates should be active users of either a high-level software programming language (ideally C++) or a hardware description language (VHDL or Verilog®).
Please contact Doulos direct to discuss and assess your specific experience against the pre-requisites.
Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include:
Learn about the differences between C and C++
Header files • Function overloading • Operator overloading • Pass-by-reference • const reference • Default arguments • I/O streams • Namespaces • Stream manipulators • Stream operator overloading • Standard string class • Stringstreams • Static, automatic, and dynamic storage • new and delete
Learn the principles of object-based design • Classes and objects • Inline members versus separate compilation • Public and private class members • Member functions • Scope resolution
Constructors • Destructors • Copy constructors • Initialization versus assignment • Pointers versus objects • The assignment operator • this • Constant objects and members
Learn to make the most of the built-in standard classes • The C++ standard library • Vectors versus arrays • Common vector operations • Iterators
Master the subtleties of object-oriented programming in C++
Class relationships • Subobjects versus pointers • Initializing members • Initializing const members
Learn to exploit the power of object-oriented programming • Derived classes • Inheritance • Protected members • Up- and down-casting
Delve deeper into object-oriented programming techniques • Overriding methods • Virtual functions • Polymorphism • Identifying types at run-time • Examples from SystemC • Abstract base classes
Advanced C++ features used in the SystemC class libraries • Function templates • Class templates • Examples from SystemC • Implicit conversions • User-defined conversions
Friends • Static members • Order of initialization • Multiple inheritance • Exceptions
Become proficient in using the features of SystemC
Learn the background to SystemC and how SystemC fits into the system-level design flow • The architecture of the SystemC release • The benefits and risks of adopting SystemC • The objectives of transaction-level modeling
Learn how SystemC source code is structured and how to organise files • SystemC header files and namespaces • Compiling and executing a SystemC model
How to describe the structural connections between modules • Modules • Ports • Processes • Signals • Methods • Primitive channels • Module instantiation • Port binding
Describing concurrency and the passage of time • SC_METHOD • SC_THREAD • Event finders • Static and dynamic sensitivity • Time • Events • Clocks • Dynamic processes
Gain an insight into how SystemC manages the scheduling of processes and events • Starting and stopping simulation • Elaboration and simulation callbacks • The phases of simulation • Event notification • wait and next_trigger
Learn to apply SystemC to modeling data, communication and busses
Data types for bit-accurate and hardware modeling • Signed and unsigned integers • Limited and finite precision integers • Assignment and truncation • Bit and part selects • Bit and logic vectors • Hexadecimal numbers
Learn about the facilities provided by SystemC to ease debugging and diagnostics • The report hander • Customizing report actions • Writing trace (vcd) files
Learn how channels are used to abstract communication and create fast simulation models • Hierarchical, primitive and minimal channels • Interface method calls • SystemC interfaces • Port-less channel access • The SystemC object hierarchy • The class sc_port • How to make the most of ports, channels and interfaces • sc_export
Learn the techniques required to write and use bus models in SystemC • Master and slave interfaces • The execution context of interface method calls • Blocking and non-blocking methods • Using events and dynamic sensitivity within channels • Multi-ports • Port binding policies
Exploration of the application of Transaction-Level modeling
sc_signal_resolved • register_port • sc_process_handle • Event finders • default_event • pos vs. posedge vs. posedge_event • sc_event_queue • request_update and update • Passing arguments to spawned processes • terminated_event • sc_set_stop_mode
Transaction Level Modeling • Virtual platforms • The architecture of TLM-2.0 • TLM-2.0 coding styles • The interoperability layer • TLM-2.0 utilities • Initiator, target, and interconnect • Initiator and target sockets • Generic payload • Response status
Software execution and simulation • The time quantum • b_transport • Timing annotation • Temporal decoupling • The quantum keeper • Base protocol rules • DMI • Simple sockets • Extensions • Interoperability
Fixed point word length and integer word length • Quantization modes • Overflow modes • Fixed point context • The type cast switch • Utility methods
RTL versus behavioural synthesis technology • The work of the OSCI synthesis working group • Synthesizable data types • Synthesis restrictions • Clocked threads and resets
Introduction to and aims of SCV • Constrained random verification methodology • Extended data types to support introspection • Randomization • Transaction Recording
An overview of the latest version of SystemC, that is, IEEE 1666-2011 and SystemC 2.3
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