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This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes.
How much SystemC training do you need? Watch the video now!
SystemC Modeling using TLM-2.0 is the authoritative industry standard training class teaching the TLM-2.0 transaction-level modeling standard. This class was developed by the authors of the IEEE 1666™ SystemC® Language Reference Manual, and has been updated for compliance with the latest version of the SystemC and TLM-2.0 standard.
This class builds on the Doulos Fundamentals of SystemC class to prepare the engineer for practical project readiness using transaction-level modeling with SystemC and TLM-2.0. The TLM-2.0 standard enables interoperability between transaction-level models from different sources while allowing the fast simulation speed necessary for virtual prototyping. This class gives delegates the opportunity to hear the features of TLM-2.0 explained by people who worked at the heart of the standard development, and to practice their skills in coding a variety of common use cases.
Unique full working examples are provided as a starting point for your own experimentation and projects.
Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.
Doulos has a world-wide lead in independent SystemC know-how having been active in SystemC-based methods since 2000. We have delivered SystemC training and support to engineers in more than 500 companies world-wide - including direct involvement with methodology and tool developers in such companies as Arm, Cadence, Seimens EDA and Synopsys.
Hardware, software and systems engineers who have a good working knowledge of C++ and SystemC and want to learn to use the OSCI TLM-2.0 standard.
There are three necessary steps in the learning path to effective SystemC usage:
Hardware or embedded software engineers with a background in Verilog, VHDL or C, will usually need to attend both Comprehensive SystemC and SystemC Modeling using TLM-2.0 within the space of a few weeks or months.
Engineers with an excellent working knowledge of C++ (or some other object-oriented programming language) may be able to fast-track some of the SystemC learning requirement. Please contact Doulos direct to discuss and assess your specific experience against the pre-requisites.
Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include:
If you would prefer a paperback version of your Doulos Golden Reference Guide, this can be purchased from the Doulos online shop.
Role of SystemC and TLM • Evolution of TLM within OSCI • TLM requirements and use cases • Coding styles • TLM-2.0 structure and architecture • Interoperability layer • Utilities • The OSCI TLM-2.0 release kit and documentation
Initiators, targets, and interconnect • Initiator and target sockets • Pass-by-reference • Forward and backward paths • TLM-2 core interfaces • Blocking versus non-blocking transport • Standard socket classes • Socket binding • Introduction to the generic payload and base protocol
Blocking Transport Interface
Blocking transport interface • Timing annotation • Temporal decoupling • Quantum keeper • Global quantum • Synchronization-on-demand • Loosely-timed coding style
Generic payload attributes • Mutability • Command, address and data attributes • Byte enables • Streaming • Response status • Generic payload memory management
Non-blocking Transport Interface
Non-blocking transport interfaces • tlm_sync_enum • Forward, backward and return paths • Phases • AT timing model • Base protocol rules • Early completion • Pre-emption • AT timing annotation • Payload event queues • Approximately-timed coding style • Request and response exclusion rules • Back-pressure • AT interconnect
Simple sockets • b/nb conversion • Tagged sockets • Multi-sockets • Coding interconnects and address translation • Hierarchical binding • Passthrough sockets
Direct Memory and Debug Transport Interface
Direct memory versus debug interfaces • Direct memory interface • DMI transaction type • DMI descriptor • Rules for granting and denying DMI • Generic payload DMI hint • Address translation for DMI transactions • Debug transport interface • Debug transport transaction type
Kinds of extension · The extension mechanism • Generic payload extension methods • Extension base class • Low-level extension programming • deep_copy_from • update_extensions_from • Extension memory management • Auto extensions • Sticky extensions • Memory-manager-agnostic extensions • Instance-specific extensions
TLM-2 endianness principles • Organisation of the data array • Mixed-endian systems • Address alignment issues • Part-word transfers • Width conversions • Endianness helper functions • Endianness conversion functions • Arithmetic mode • Byte order mode • Tuning for simulation speed
tlm_phase • Extended phases • Ignorable phases • Protocol types • tlm_base_protocol_types • Defining new traits classes • Guidelines for protocol creation • Bridges • Bus snooping using DMI extensions
Analysis interface • Analysis port • Subscribers • When to deep-copy transaction objects
Source code examples to use in your own projects • AT initiator types • AT target types • Permutations of the forward, backward and return paths • Full AT interconnect implementation • Implementing exclusion rules and transaction queuing • Mixed AT/LT components • Base protocol checker • Atomic operations and transaction locking using extensions
|24 Jul 2023||ONLINE Americas||Enquire|
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