SystemVerilog for New Designers SELF-PACED

SystemVerilog as a first or second language for FPGA or ASIC design

Standard Level - 30 hours (estimated completion time)
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PLEASE NOTE: This is an ONLINE SELF-PACED course.

Course Overview

SystemVerilog for New Designers Self-Paced prepares the engineer for practical project readiness for FPGA or ASIC design, including RTL synthesis, block-level test benches, and FPGA design flows. The course is suitable for those with existing experience of Verilog or VHDL, as well as those who are learning SystemVerilog as their first hardware description language.

Workshops comprise approximately 50% of the estimated completion time and are based around carefully designed exercises to reinforce and challenge the extent of learning. All course exercises and worked solutions are provided on the free and open EDA Playground platform. All the exercises, scripts, example designs, and constraint files are downloadable to use, adapt and extend on your own projects.

Leading tools supported by this course on the EDA Playground platform include:

Simulation

Aldec Active HDL™ & Riviera-PRO™
Cadence Xcelium®
Siemens EDA Questa®
Synopsys VCS®

Synthesis

Siemens EDA Precision® RTL

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Who is it for?

Digital hardware design engineers who wish to learn how to use SystemVerilog for FPGA or ASIC hardware design at the register-transfer level (RTL) and for block-level verification.

What will you learn?

The SystemVerilog language concepts and constructs essential for FPGA and ASIC design
How to write SystemVerilog for effective RTL synthesis
How to target SystemVerilog code to an FPGA device architecture
How to write simple and efficient SystemVerilog test benches
The tool flow from SystemVerilog through simulation and synthesis
How to write high quality SystemVerilog code that reflects best practice in the industry
How to write re-usable, parameterisable SystemVerilog code by exploiting parameters
How to run gate-level simulations

Pre-requisites

A good working knowledge of digital hardware design, or have attended Essential Digital Design Techniques (or equivalent training). Existing experience of Verilog or VHDL is helpful, but no previous SystemVerilog, Verilog or VHDL knowledge is required.

Course materials

Doulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:

Multimedia presentations accompanied by detailed notes complementing the spoken narrative
Downloadable workbook full of practical examples and solutions to help you apply your knowledge
Access to course exercises and worked solutions on the free and open EDA Playground platform

Structure and Content

Design Principles and Tools
Hierarchical Design • Design Tools • Levels of Abstraction • Design Flow • Synchronous Design • FPGA Structure • Compilation • Compilation Unit Scope • Gate-level Simulation • Design Flow for PLD Design • Design Flow for IC Design

Basic Language Features
Modules • Variables & Time • Numbers • Arrays and Always

Basic Design Processes
Always and Synthesis • If, Case and Loop

Further Language Features
Wires and Variables • Operators • Tasks and Functions • Macros, Parameters and Generate • Hierarchical Names • Other Topics

From Verilog to SystemVerilog
Introduction to SystemVerilog • Programming Language Features • SystemVerilog Data Types

Interfaces
Interfaces • Bus-Functional Modeling

SystemVerilog RTL processes and types
SystemVerilog RTL Processes • SystemVerilog RTL Types

Implementing Finite State Machines (FSMs)
Implementing Finite State Machines - Introduction • An Example Finite State Machine • First Finite State Machine implementation • Separate combinational and sequential logic • One-hot State Machines • Registered Outputs • State Encoding • Unreachable States

Further RTL
Further RTL - Introduction • Conditional Operator • Vector Arithmetic • Arithmetic with Signed Types • Resource Sharing • Synthesis of For Loops • Synthesis of Memories • Synthesis of Functions • Task Reference Arguments • Synthesis of Tasks

File Handling
Writing Files • Reading Files

Clocking Blocks
Clocking Blocks

Advanced Verification Techniques
Randomization • Coverage

Working with Data
Arrays and Queues • Other Language Features

The Direct Programming Interface (DPI)
The Direct Programming Interface

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SystemVerilog for New Designers Self-Paced

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