Introduction to UVM
What is UVM? • Why UVM? • Versions of UVM • Constrained Random Verification • Random Stimulus (Reminder) • How Much Coverage? (Reminder) • Tests versus Verification Environment • The Component Hierarchy • UVM Class Hierarchy • Transaction Level Modelling • Simulation Phases • The Factory • Layered Sequential Stimulus • Virtual Sequences • Hierarchical Configuration • Doulos – Easier UVM • Subject Areas for the UVM Adopter
Getting Started with UVM
Simple Testbench Architecture • Sequence Item Class • Sequence Class • Sequence versus Sequencer • Driver • Driver run_phase Task • Driver versus Monitor • Monitor Class • Monitor run_phase Task • Analysis Port • Agent Class Build Phase • Agent Class Connect Phase • Environment Class • Starting Sequences in More Detail • Test Class • Packages and Classes • Configuration Database • Top-Level Module
Reporting
Severity, id, Message • The Four Basic Reporting Macros • Using Verbosity • Setting Severity Actions • Severity and Actions • Setting id Actions • Scope of Actions • Reports Outside of UVM Components • uvm_root and uvm_top• Global Report Actions • Reports from Sequences • Report Context • Redirecting Reports to Log Files • Changing the Verbosity Level • Max Quit Count
Transaction-Level Modeling
TLM Connections • TLM Ports, Exports, and Imps • Child Port Connection • Child Export Connection • Implementing an Export • Push vs Pull Connections • Sequencer-Driver Connection • Sequence-Driver Protocol • Analysis Ports • Monitor with Analysis Port (Reminder) • Subscriber Class • Connecting Analysis Ports • Copying and Comparing Transactions
Interlude
Constraining Transactions • Generating Write and Read Transactions • uvm_do • Version Macros • Macros for Upgrading to IEEE 1800.2 • get vs get_next_item • Sequence-Driver Interaction • Print Topology • Finish on Completion • Debugging Connections
Scoreboards
Checking and Coverage • Reference Model and Scoreboard • Environment Class • Reference Model • Scoreboards • uvm_analysis_imp_decl • Matching the Transactions • Using Field Macros to Ignore Fields • Functional Coverage • Architectural Flexibility • Monitoring Internal States of the DUT • HDL Backdoor Access
The Factory
Factory Overrides • Where to do Factory Overrides • Kinds of Factory Override • Command Line Processor • uvm_set_type_override • More Command Line Flags • get_args • Wildcard Paths • uvm_component_param_utils • Registering Abstract Classes • factory.print
The Configuration Database
Constrained Random Generation • The Configuration Database • The Three Usual Ways to Call set/get • Getting and Setting Values • Wildcard Paths • Multiple Configuration Tables • Configuration Class • Randomize Configuration Object • Configuring the Component Hierarchy • Agent Configuration • Sequence Configuration • Debugging Configuration Settings
Objections
Objection Mechanism • Raising and Dropping Objections • +UVM_OBJECTION_TRACE • Objections within Sequences • pre_start, post_start, do_kill • Raising / Dropping Objections Per-Cycle • Drain Time versus Time-out
Methods of uvm_object
Field Macros • uvm_field_utils and uvm_component_utils • Field Macro Flags • print and sprint • Radix and Printers • Overriding the Methods • Overriding do_compare • Field Macros and Overridden Methods • Using Policy Objects • Overriding do_pack • Packing Bits and Bytes • Calling pack in a Driver • Transaction Recording • Marking the Start & End of Transactions
Sequences
uvm_sequence • Starting a Sequence from a Component • Starting a Sequence from a Sequence • uvm_do • Sequence Macros – Legacy UVM 1.2 • Sequence Macros – IEEE 1800.2 • Sequence-Driver Interaction • Overriding the Callbacks • Sequence Callbacks • Sequence-of-Sequences • Sequence Control Knobs • Nested Sequences • Configuring a Sequence • Configuration of Control Knobs
Virtual Sequences
Virtual Sequences and Sequencers • Virtual Sequence • Virtual Sequencer
Layering Sequences and Agents
Layering Sequencers • Layering Agent • Transactions • High-Level Sequence • Layering Sequence • Layering Monitor • Starting with a Virtual Sequence • Factory Overrides
Responses
To Send Information Back Upstream • Request versus Response versus Monitor • The Driver Response • Matching Requests and Responses • Pipelined Request/Response in the Sequence • Pipelined Request/Response in the Driver • Layering Agents • Multiple Agent Stacks • try_next_item in the Driver
Events and Barriers
Edge-Sensitive Event • Level-Sensitive Event • Other Event Functions • Passing Data with Event Trigger • Event Pools • Barriers • uvm_barrier_pool
Advanced Sequencer Topics
Interleaved Sequences • Sequence Priority • The Arbitration Queue • Setting the Arbitration Algorithm • Arbitration Algorithms and Priority • User-Defined Arbitration Algorithm • Sequencer Lock • Lock versus Grab • The UVM Sequence Library • Sequence Library = Fancy Sequence • Controlling Sequence Selection • Setting Properties with the Configuration Database
Register Layer
UVM Tests and DUT Registers • UVM Register Layer • Register Layer Architecture • UVM Register Layer Features • Register Layer Organisation • Accessing Registers By Name • Integrating the Register Model • Frontdoor Register Access • Backdoor Register Access • Mirroring • Updating • Register Model • An Example - Serial I/O • Serial I/O Memory-Mapped Registers • Unit-Level Register Model Integration • Define Registers and Fields • Configure the Register • Create the Register Block • Build the Registers • Create the Address Map • Register Adapter • Provide a Driver Response • Using Byte Enables • Integration into the Environment • Accessing the Register Model • Register Test Case • Random Register Testing • Built-in Sequences • Using Built-in Tests
Advanced Register Topics
Indirect Register Access • System-Level Register Model Integration • Front Door Sequence Integration • Define a Front Door Sequence • Setting a Front Door Sequence • Responses • Predictor • Integrating a Predictor • Direct Access Through Back Door • Adding the HDL Path • Using the Backdoor • HDL Backdoor Access • HDL Backdoor Access Routines • Memory Access within an Address Map • Adding Memory to an Address Map • Coverage Models • Instantiate Coverage Model during Build • Enable/Disable Coverage • Coverage in a Register Block • Sample Method in a Register Block • Enabling Coverage • Special Register Behaviours • Register Access Flow and Callbacks • Example: Register Aliasing
Appendix - Further Detail
Transaction Level Modeling • Blocking put, get, and peek • Blocking versus Non-Blocking Methods • uvm_tlm_analysis_fifo • Subscriber with uvm_tlm_analysis_fifo • Subscriber with FIFO Implementation • Parameterized Interfaces • Interfaces • Parameters & Interfaces – What's the Issue? • Components and Configuration • Component Hierarchy Introspection • find versus find_all • Globs versus Regular Expressions • Automatic Configuration • Overriding Agent get_is_active • Objections • Extending a Phase • Propagating Objections • set_propagate_mode • Sequencers • is_relevant • Push Sequencer and Driver • Push Driver Implementation • Callbacks • Callback Base Class • Insert Callbacks into Component • Implement Specific Callbacks • Add the Specific Callback • Event Callbacks • UVM Event Callbacks • Event Callback Class • Register Callbacks from Component • The Report Catcher • Registering Report Catchers • Hearbeat • uvm_heartbeat • Adding Heartbeat to Driver • Enabling Heartbeat from Test • Memory Manager • Memory Access within an Address Map • Adding Memory to an Address Map • Memory Allocation • UVM Memory Allocation Manager • Memory Access Sequence
Appendix - UVM Run-Time Phasing
Motivation • Background • The Common Phases of UVM • Phase Methods & Objects • The UVM Run-Time Phases • Default Synchronization • Phase Method Synch • Domains • Unsynchronized Domains • Explicit Synchronization • Synchronized Phases • User-Defined Phases • Extended Schedule • Add after_phase • Add before_phase • Add with_phase • A Schedule from Scratch • set_domain / define_domain • Overriding define_domain • Calling set_domain • Start and End of each Phase • phase_started • phase_ready_to_end • phase_ended • Making Sequences Phase-Aware • Reactive Stimulus • Phase Jumping • VIP Creation • VIP Integration • User-Defined Phases • Phase Ordering • Recommendations
Appendix - UVM 1.2
Language Changes • UVM Type Aliases • Configuration • uvm_*_comparator • Accessor Methods • Policy Classes • copy • printer • uvm_printer_knobs • pack • do_execute_op • uvm_object call / callback sequence • uvm_field_op • Policy Extensions • uvm_default_coreservice_t • Extending uvm_default_coreservice_t • uvm_init • uvm_run_test_callback • unlock
