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Essential Verification Methodology
Essential Verification Methodology is a comprehensive methodology course aiming to provide an overview of the functional verification process and the current range of technologies available to implement it successfully.
The course has no bias towards any particular design or verification language or EDA tools from any particular manufacturer. As such, it could be used as a precursor to a number of other Doulos verification-related courses, such as 'Comprehensive SystemVerilog' or 'Expert VHDL', each of which provides in-depth training and hands-on workshops in the corresponding language and methodology.
Pencil-and-paper exercises are included to reinforce and challenge the extent of learning and comprise approx. 15% of class time.
Delegates require no prior involvement in verification, but should be familiar with the digital design process. Any knowledge of a hardware description language (HDL) or any other verification-associated languages, such as e or PSL, would be helpful but by no means essential.
Doulos course materials are renowned for being the most comprehensive and user friendly available. Course fees include:
Definitions, terminology • Functional verification flow and methods • Linting • Simulation • Debugging • Modelling • Coverage • Assertion-based verification • Formal methods
Verification Plan: Creation and maintenance • Verification strategy • Test definition, generation and execution • Re-usable verification IP • Milestones and code reviews • Regression and stress testing • Verification metrics and bug-tracking
HDL testbenches • Testbench architecture • Bus Functional Models and data modelling • Testbench automation • Hardware Verification Languages (HVLs) • Object-oriented and aspect-oriented programming • Stimulus generation, directed, random and constrained-random • Response checking and self-checking testbenches • Variable latency, FIFOs and scoreboarding • Coverage-driven methodology and types of coverage
Properties, their definition and use • Temporal properties • Assertions • Authoring of properties and assertions • Observability and functional coverage • Re-using properties
Definitions, motivation and terminology • Equivalence checking • Property checking • Coverage • Safety, liveness, invariant • Assumptions • Dynamic formal verification
Hardware acceleration • Emulation and In-Circuit-Emulation (ICE) • FPGA Prototyping • Observability of internal design nodes • Synthesizable assertions
Boolean algebra • Temporal logic: CTL and LTL • Fairness
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