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Debugging Features of UVM

Wednesday June 15 2022

1 hour session (All Time Zones)
Presenter: Doug Smith

Senior Member Technical Staff

Asia and Europe

Wednesday, June 15, 2022

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)


Americas

Wednesday, June 15, 2022

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)


A UVM testbench is a large and complex piece of software. At some stage, like any other large and complex piece of software, a verification environment written using UVM is going to require debugging. There are various debugging features built into UVM to help with this.

In this webinar Doulos Senior Member Technical Staff, Doug Smith, explores the various features in UVM to help you debug your UVM environment, your test cases, and your design under test.

Topics include:

  • Debugging the Testbench
  • Debugging Stimulus
  • Debugging the Design

At the end of the webinar Doug will also look at an example of tool support features for debugging UVM using the Cadence® Xcelium™ Logic Simulator.


Doug Smith

Doug Smith - Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.


Attendance is free of charge

If you have any queries, please contact webinars@doulos.com


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Visit www.doulos.com/knowhow


UVM training available from Doulos:

Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.