Debugging Features of UVM

Webinar Overview:

A UVM testbench is a large and complex piece of software. At some stage, like any other large and complex piece of software, a verification environment written using UVM is going to require debugging. There are various debugging features built into UVM to help with this.

In this webinar Doulos Senior Member Technical Staff, Matthew Taylor, explores the various features in UVM to help you debug your UVM environment, your test cases, and your design under test.

Topics include:

• Debugging the Testbench
• Debugging Stimulus
• Debugging the Design

At the end of the webinar we will also look at an example of tool support features for debugging UVM using the Cadence® Xcelium™ Logic Simulator.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com

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