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Deep Dive into the UVM Register Layer

1 hour session (All Time Zones)
Presenter: John Aynsley

Co-Founder and Technical Fellow

Asia and Europe

Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)


Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)

Webinar Overview:

This webinar focusses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave, such as non-linear addressing, burst access mode, registers accessed through an embedded CPU and quirky registers.
The following topics will be covered:

  • Using user-defined front doors and back doors to extend the capabilities of the register layer beyond sending simple request and response transactions to the DUT.
  • Understanding the role played by the predictor in updating the register model and how to use the predictor in the presence of user-defined front doors.
  • Using register callbacks to model quirky register behaviors, the side-effects of register reads and writes, and aliased registers.
  • Exactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation.

Used together, these topics provide an important set of mechanisms for extending the capabilities of the register layer in many useful ways.

We will show code examples that can be run in the Cadence® Xcelium™ Parallel Simulator.

John Aynsley

John Aynsley is Doulos Co-Founder and Technical Fellow. John will present this webinar which consist of a one-hour broadcast with interactive Q&A available to attendees throughout.

Attendance is free of charge

If you have any queries, please contact

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