1 hour session (All Time Zones)
Presenter: John Aynsley
This webinar focusses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave, such as non-linear addressing, burst access mode, registers accessed through an embedded CPU and quirky registers.
The following topics will be covered:
Used together, these topics provide an important set of mechanisms for extending the capabilities of the register layer in many useful ways.
We will show code examples that can be run in the Cadence® Xcelium™ Parallel Simulator.
John Aynsley is Doulos Co-Founder and Technical Fellow. John will present this webinar which consist of a one-hour broadcast with interactive Q&A available to attendees throughout.
Attendance is free of charge
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