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1 hour session (All Time Zones)
Presenter: Matthew Taylor

Doulos Senior Member Technical Staff

Asia and Europe

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)


Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

Webinar Overview:

The UVM Register Layer is a complex system for describing and integrating registers in a UVM environment.

This webinar gives an introduction to the purpose of the UVM Register Layer and the concepts behind it. It will then show how a register generator can generate the majority of the required code, using Cadence's Reg Verifier as an example. Finally, it will outline how to integrate your bus adapters and run some of the built-in test sequences.

The webinar will cover:

  • An overview of UVM and the UVM Register Layer
  • The Register Model
  • Integrating the Register Model into the Testbench
  • Running tests using the Register Model
  • And some additional features of the Register Layer including frontdoor & backdoor access, mirroring, updating and built-in sequences

The webinar will feature code examples running in Xcelium from Cadence.

Matthew Taylor

Matthew Taylor , Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Attendance is free of charge

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