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Getting Started with UVM

1 hour session (All Time Zones)
Presenter: Matthew Taylor

Doulos Senior Member Technical Staff

Asia and Europe

Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)


Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)

Webinar Overview:

This webinar will introduce you to the Universal Verification Methodology.

The aim is to provide you with a base to start learning the rest of UVM, starting at why you would want to use it and the key components of a UVM test bench. The webinar will provide an overview of the DUT interface and Sequencer-Driver communication.

The webinar will help you to understand:

  • the class hierarchy
  • simulation phases
  • transaction-level communication
  • sequences and sequencers
  • drivers
  • the factory
  • the configuration database
  • objections 

This webinar is run in partnership with Siemens EDA and will feature code examples running in the Questa Advanced Simulator. The aim is to help you go on to learn the rest of UVM or to understand the rationale and working of automatically generated UVM code such as that produced by the Siemens EDA UVM Framework and Doulos' Easier UVM code generators.

Matthew Taylor

Matthew Taylor , Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Attendance is free of charge

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