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Expert VHDL Verification ist ein intensives Aufbautraining. Entwickler steigern mit diesem Training die Produktivität durch den Ausbau ihrer VHDL-Codierungs- und -anwendungs-fähigkeiten. Der Fokus des Kurses liegt auf Testbenches und den neuesten Verifikationstechniken wie und Transaction Level Verification(TLV) und stellt die OSSVVM und UVVM- Methoden vor.
Die Workshops basieren auf sorgfältig durchdachten Übungen mit dem Ziel, das Erlernte im Zusammenhang mit den neuesten VHDL Tools, Praktiken und Methoden anzuwenden und zu festigen. Dieser Praxisteil nimmt etwa 50% der Unterrichtszeit ein. Expert VHDL Verification bildet die letzten 3 Tage des kompletten 5-tägigen Doulos Expert VHDL Kurses.
Design- und Verifikations-Ingenieure, die sich mit VHDL Testbench-Entwicklung oder Verhaltensmodellen zum Nutzen von funktionaler Verifikation beschäftigen
Um den größten Nutzen aus dem Training ziehen zu können, ist die Teilnahme am Doulos Comprehensive VHDL Kurs oder einem vergleichbaren Training erforderlich.
Die Doulos Kursunterlagen sind für ihren umfassenden Informationsgehalt und die äußerst benutzerfreundliche Präsentation allgemein bekannt. In ihrem Aufbau, Inhalt und ihrer Themenbehandlung sind sie einzigartig im HDL-Trainingsbereich, was sie zu begehrten Nachschlagewerken hat werden lassen. In den Kursgebühren sind enthalten:
What Is Verification? • Approaches to Verification • Verification Strategy • What to Verify? • Towards a Verification Plan • Don't Plan Everything • Identify Testcases • Verification Metrics • Coverage • Including Functional Coverage • Coverage Driven Verification • From Features to Tests • Checking • Verification Planning Revisited • The Basic Testbench • Verification Environment • Verification Methodologies • VHDL Methodology • Design for Verification • Glass Box Testing • Analysis to Choose Tests • Boundary Conditions & Corner Cases • Black Box Testing • Regression Testing • Stress Testing • Different Sorts of Stimulus
Using Abstraction in a Testbench • Subprograms • Procedures • Parameter Class, Mode, and Type • Subprogram Overloading • Signal Parameters • Functions • Subprograms in Packages • Impure functions • Protected types • Protected type body • Declaring a Shared Variable
The Basic Testbench • TEXTIO Output • Procedure READ • When READ Goes Wrong • Converting Values to Text Strings • Opening and Closing Files • Testing the File Open Status • Managing Text Files • Package STD_LOGIC_TEXTIO • Using Built-in Files • Reading Variable Length Data • Files Without Textio • Binary Files • VHDL-2008 File IO
Structuring Testbenches • Build the Complete Testbench • Monolithic Testbenches are Inflexible • Hide DUT Interface from Testcase • Layered Architecture • Transaction Level Testcase • Making a Transaction in VHDL • Accessing the Fields • Communicating Transactions • A Simple Example • What is a (VHDL) Transaction? • Interfacing Without Events • Generating Transactions • Using Procedures with Signals • A Systematic Approach • Non-blocking Procedures • Bus Functional Modelling • Bus Functional Model • Bus Functional Model Using Get • Synchronization • Synchronization Channel • Summary
Bus Functional Modelling • Wait Statements • Wait Statements and Time • Inspecting the Event Queue • Example SRAM Timing • Setup Time Check • Hold Time Check • Combined Setup / Hold Time Check • Pulse Width Check • Entity Declarations • Passive Processes • Using Vital Packages • Setup/Hold Check With Vital • What About Transactions? • Concurrent Signal Assignments • Drivers • How to "See" Drivers • Multiple Driver Issues • Longest Static Prefix • Sequential Signal Assignments • Inertial Delay • Identical Successive Assignments • Inertial Delays • Inertial and Transport Delays • Sampling Data - RTL • Postponed Processes
Checking Results • Variable Latency • Arrays of Records • Queues • VHDL Queue Implementation • Using Queues • Coping with Out-of-Order Completion • Scoreboarding • Dynamic Memory Allocation • Access Types • Allocators • Deallocating Memory • Writing to a FIFO • Rrading from a FIFO • Pointer Problems • Behavioural Modelling Example • Modelling the 2-wire Bus • Two Wire Slave Model • Protocol Implementation • Data Generation • Slave Procedure • Modelling State
Verification - Reminder • Random Stimulus • Constraining Random Stimulus • Random Sequence of Valid Actions • Functional Coverage • Where Am I? • Concurrent Procedures • Coverage Procedure • Calling Coverage Procedures • Why Use Path Parameter?
Completing our Methodology • Monitoring Internal Signals • Monitoring Internal Signals - VHDL-2002 • External Names • Monitoring Internal Signals - VHDL-2008 • Force and Release • The Objection Mechanism • Implementing Objection • Resolution Functions • Implementing Custom Objections • The Stop and Finish Procedures • Run-time Configuration • Implementing Run-time Configuration
What is OSSVVM? • Randomization • Seed Management • Functional Coverage • Sampling • Specifying Bins • Specifying a Minimum Hit Count Per-Bin • Specifying Cross Bins • Specifying Ignore Bins • Displaying Coverage • Non-Repeating Randomize • Defining Explicit Weights • Weight by Coverage Shortfall • Logging • Redirecting to a Log File • Alerts • Stop Count • Disabling Alerts • Conditional Alerts • Hierarchical Alerts • Other Packages
What is UVVM? • Utility Library • Logging and Verbosity Control • Outputting Log Messages • Controlling Log Messages • Message IDs • Redirecting Log Messages • Alerts • Controlling Alerts • Reporting Alerts • Checks • Awaits • String Handling • Randomization • Signal Generators • Synchronization • BFM Common Package • Warnings • UVVM VVC Framework • UVVM Structure • UVVM Test Harness • UVVM Test Bench • Test Sequencer • UVVM Command Distribution • Example Command Distribution Methods • UVVM VHDL Network Model • VIP • Feature Comparison
| Course Dates: | |||
|---|---|---|---|
| June 5th, 2019 | Munich, DE | Enquire | |
| June 19th, 2019 | Ringwood, UK | Enquire | |
| July 10th, 2019 | Ankara, TR | Enquire | |
| July 31st, 2019 | San Jose, CA | Enquire | |
| September 25th, 2019 | Ringwood, UK | Enquire | |
| October 9th, 2019 | Munich, DE | Enquire | |
| October 9th, 2019 | Ankara, TR | Enquire | |
| November 14th, 2019 | Boston, MA | Enquire | |
| November 14th, 2019 | Columbia, MD | Enquire | |
| December 11th, 2019 | San Jose, CA | Enquire | |
| indicates CONFIRMED TO RUN courses. | |||
Friday December 13 2024
1 hour session (All Time Zones)
This webinar is aimed at hands-on hardware or software engineers who might know Verilog or C but have no previous experience of SystemC. It will explain what you need to know to be successful with SystemC.
Tuesday December 17 2024
1 hour session (All Time Zones)
This webinar will walk through the design process for using AMD Kria SOMs, including the use of Vivado and Vitis.
Wednesday December 18 2024
1 hour session (All Time Zones)
This webinar explores best practices for avoiding memory issues in design and debugging memory usage issues in C and C++.
Wednesday January 15 2025
30 minute session (All Time Zones)
This webinar will explore the effects of routing vias and connector plated through holes on very high data rate signals using actual test results from as-built PCBs.
Friday January 17 2025
1 hour session (All Time Zones)
This webinar will provide some useful directions for incorporating machine learning within your next embedded project.