Technical Paper Download
The award wining paper "Using Bind for Class-Based Testbench Reuse with Mixed-Language Designs" contains copyrighted material developed by Doulos Ltd.
You are welcome to use and copy all material for private individual use. For use of any material within a commercial presentation or within a separate document for wider distribution, we request that you give due acknowledgement to Doulos as the source of that material and the copyright owner. In addition if you make enhancements or modifications to the material presented that would be of general benefit to the SystemVerilog user community we would be happy to consider its inclusion in future Doulos materials with due accreditation. Please forward any comments or enhancements to firstname.lastname@example.org, with the header "SNUG 09 San Jose Paper".
Any mention of specific organisations or their products does not imply an endorsement by Doulos of either the organisation or the product. All third party trademarks acknowledged.
Significant effort goes into building block-level class-based testbenches so reusing them in a full-chip environment has great advantages. The problem arises of which way is best to connect them into a full-chip environment that maximizes reusability. VHDL or mixedlanguage designs pose greater challenges because hierarchical references are unsupported in VHDL. Alternatively, SystemVerilog offers a simple solution with the bind command. Using bind and a few simple guidelines, a block-level testbench can be reused without modifications in a mixed-language full-chip environment.
This paper demonstrates how to structure a testbench for effortless reuse with nothing more than a single bind command.