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Using Bind for Class-Based Testbench Reuse with Mixed-Language Designs

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The award wining paper "Using Bind for Class-Based Testbench Reuse with Mixed-Language Designs" contains copyrighted material developed by Doulos Ltd.

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Abstract

Significant effort goes into building block-level class-based testbenches so reusing them in a full-chip environment has great advantages. The problem arises of which way is best to connect them into a full-chip environment that maximizes reusability. VHDL or mixedlanguage designs pose greater challenges because hierarchical references are unsupported in VHDL. Alternatively, SystemVerilog offers a simple solution with the bind command. Using bind and a few simple guidelines, a block-level testbench can be reused without modifications in a mixed-language full-chip environment.

This paper demonstrates how to structure a testbench for effortless reuse with nothing more than a single bind command.