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Order of Analysis

This is one of those topics that doesn't really relate to hardware design. However, you can't ignore this topic as it is so fundamental to simulating (and to a lesser extent, synthesizing) your VHDL designs. Anyhow, let's see how hardware-y we can make it!

Remember design units? So far we have used three of the five VHDL design units. An entity declaration is a primary design unit, as is a configuration declaration. An architecture body is a secondary design unit. An architecture is a secondary design unit of the corresponding entity declaration primary design unit. Hence,

architecture architecture_name of entity_name is
--             secondary              primary

To simulate a piece of VHDL code, you need a design environment consisting of an entity declaration and an architecture body and you also need a testbench. The testbench contains an instance of the design plus some VHDL code to apply stimuli to the design that is being simulated. In VHDL terms, the testbench is just another design entity.

OK. On to order of analysis, following on from the hardware analogy we used in the Configuration pages. In the VHDL design world, you have to create the chip package first before you can glue in the die. So, create the chip package (and put it into stores), then create the chip die (and put that into stores, too). Someone in stores will check to see that a package for the die exists, if not they'll give it back. Once you have done that, you can check the assembled chip out of stores any time you like. We'll look at checking items out of stores later on. In VHDL, checking items into stores is called analysis. In VHDL, stores is called a library (yes, in VHDL you can have lots of storerooms, hence a library not the library). So, this requires that before you analyze any architecture into a library, you must first analyze the corresponding entity declaration into the same library.

In the real world, you can goof up and put an empty chip package into stores. You can do the same in VHDL, too. Analyzing an entity declaration into a library is OK. Conversely, a VHDL architecture body must not exist alone (the VHDL storeman will lose that tiny die!); an architecture won't be put into a library unless there's already an entity declaration in the library.

To summarise, VHDL design units are analyzed into VHDL libraries. One default library is provided for you, it is called WORK. Once you have analyzed all of the design units you need for a simulation run into a VHDL library, you can run the simulation...

Simulating the MUX2

Let's suppose we have a rudimentary Unix or Windows command line interface for our VHDL simulator. The pseudo analyze command allows you to specify a VHDL library name and a filename in order to analyze the VHDL source code. We'll assume that each VHDL design unit has its own file. To analyze the VHDL in the correct order for simulation, we would enter the following pseudo analyze commands, one after the other, on the command line.

analyze -library WORK -file aoi.entity
analyze -library WORK -file aoi.v1.architecture
analyze -library WORK -file mux2.entity
analyze -library WORK -file mux2.v1.architecture
analyze -library WORK -file mux2test.entity
analyze -library WORK -file mux2test.v1.architecture
analyze -library WORK -file mux2test.v1.configuration

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