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This course covers the software aspects of designing with an Arm® Cortex®-A53 MPCore based device, highlighting the core architecture details and the Xilinx® Zynq® UltraScale+™ implementation choices. Topics include the AArch32 and AArch64 programmer's model, Arm v8-A exceptions' model, details of the available caching schemes and coherency management, memory management and the Arm memory model. Additionally, the Arm assembly section delivers the essential knowledge required for programming and debugging with T32, A32 and A64 assembly languages.
Although this training class covers both the AArch32 and AArch64 execution states implemented by the Arm v8-A architecture, a strong emphasis is put on the latest AArch64 implementation.
For teams designing applications that utilise the real-time R5 processor within the UltraScale+ MPSoC, a custom onsite training program can be delivered incorporating additional content from the Arm Cortex-R5 Software Design course.
The learning is reinforced with unique Lab exercises which are run inside a self contained virtual machine environment. This allows the student to experience a real-life and project-ready development environment without the complexity of installing complex software prior to the class. This virtual machine is for the student to keep after the training class, allowing you to further experiment with embedded software development once the class has come to completion.
Engineers who wish to become skilled in the use of an hybrid Arm Cortex-A53/R5 based System On Chip from a software and verification perspective
Engineers who are required to provide a software solution to bring a bare metal Arm Cortex-A53/R5 MPCore system to life
Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.
C programming for Embedded Systems training is also available from Doulos.
A carefully crafted combination of content from Arm, Xilinx and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Due to the exhaustive list of topics covered in this class, the material is provided as a combination of self-paced content and live in-person sessions. For on-site classes, it is possible to cover the self-paced content in a in-person sessions by adding an extra day of training delivery to the existing four.
Please speak to a member of your local Doulos sales team to discuss your custom requirement.
The self-paced content should be viewed as pre-requisite knowledge that the student will have to acquire prior to the instructor led training. The modules are fully indexed videos, browsable slide by slide and accessible both on a computer or a portable device. No software installation is required for accessing the video content.
The self-paced modules are accompanied by numerous hands-on exercises found inside the same virtual machine provided for the main instructor led training class.
Overview • Processing System • CCI General Configuration • AXI ACE and DVM extensions • SoC Implementation Choices • Development Tools
Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
Load/Store • Data Processing • Flow Control • Misc • DSP
Introduction • Interrupts • Abort Handlers • SVC Handlers • Undef • Handlers • Reset Handlers
Introduction • Twin CPU support • L1 memory system • Error detection • Misc
Memory Management Introduction • Access Permissions and Types • Memory Protection Unit (MPU) • Optimizations & Issues
Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model
Core pipelines • Configuration options • Branch prediction • Cache overview • Data cache coherency • Memory management • Micro-architectural features • Interrupts and bus interfaces • Debug and timers • Big-little
Registers • Loads and stores • Data processing and control flow • Scalar floating-point and SIMD
Synchronization in Armv8-A • Local and Global Exclusive Monitors
The AArch64 exception model • Interrupts • Synchronous exceptions • SError • exceptions • Exceptions in EL2 and EL3
Booting an Armv8-A processor in AArch64 • Booting multi-core and multi-processor systems • Real-world booting
General Cache Information • Cache Attributes • Cache Maintenance Operations • Cache Discovery
Memory Management theory • Stage 1 Translations at EL1/0 • Translations at EL2 / EL3 • TLB maintenance
Types • Attributes • Alignment and endianness • Tagged pointers
Data barriers • Instruction barriers
Context Switching • Modifying Translation Tables • Privilege Escalation Protections • Timers
Why do we need a Secure environment? • Software stack • System architecture
Introduction to coherency • Coherency details - multi-core processors • Coherency details - multi-processor systems
What is virtualization? • Arm virtualization support • Memory management • Exception handling
Arm core power modes • Power control • Arm multi-core processor power modes • Power state coordination
Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues
Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries
Introduction to Debug • Types of Debug • Debug Facilities • External Debug • Self-hosted Debug • CoreSight • Debug Features • Trace
Introduction • Performance Monitoring Hardware: PMU • Cycle Accurate Trace: Trace • Macrocells • Streamline Performance Analysis
Interrupt Controller • System MMU • TrustZone Address Space Controller • Generic Timer
The learning is reinforced with unique Lab Exercises using an Armv8-A 64 bit instruction set simulator and covering assembly programming, exception handling and setting up the caches and MMU.
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