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Arm Cortex-R5 Software Design
This training course covers the issues involved in developing software for platforms powered by the Arm Cortex-R5 processor.
Software engineers designing applications for platforms based around the Arm Cortex-R5 processor Core. Much of the content is relevant to users of 3rd party tools but we cannot undertake to cover them in any detail.
Delegates should have a basic understanding of microprocessor systems and be familiar with assembler or C programming. A basic awareness of Arm and experience of embedded system development is helpful, but not essential.
This class uses training materials developed by Arm®
Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions
Arm DS-5 • Tool Licensing • GNU and ABI • Debug Interfaces
Load/Store Instructions • Data Processing Instructions • Flow Control • Miscellaneous • DSP
Exceptions overview • Interrupts sources and priorities • Abort Handlers • SVC Handlers • Undef Handlers • Reset Handlers
Cache basics • Caches on Arm processors • Tightly Coupled Memory (TCM) • Optimization consideration
Memory Management Introduction • Access Permissions and Types • Memory Protection Unit (MPU) • Optimizations & Issues
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data issues
Linking Basics • System and User Libraries • Veneers and Interworking • Linker Optimizations and Diagnostics • Arm Supplied Libraries
Invasive Debug • Non-Invasive Debug • PMU • Trace
Introduction • Twin CPU support • L1 memory system • Error detection • Instruction set changes
Mixing C/C++ and Assembler • Stack Issues • VFP/NEON • Advanced Building Facilities Embedded Software Development
An "Out-of-the-box" build • Tailoring the C library to your target • Tailoring image memory map to your target • Reset and Initialization • Further memory map considerations • Building and debugging your image
Processor Power Consumption • Power Modes • NEON and MPCore
Debug Logic Overview • Debug Logic Features • Tools use of Debug Logic • Trace Logic Overview • Debug vs. Trace • System Level Debug Infrastructure • CoreSight Introduction CoreSight Debug • CoreSight Trace
The learning is reinforced with unique Lab exercises using the QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life. Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on a combination of GNU compilation tools, GDB and an instruction set simulator used for fast prototyping. Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/DDD and QEMU).
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