Arm Cortex-R4 Software Design

Software engineers designing applications for platforms based around the Arm Cortex-R4 processor Core.

Delegates should have a basic understanding of microprocessor systems and be familiar with assembler or C programming. A basic awareness of Arm and experience of embedded system development is helpful, but not essential.

This class uses training materials developed by Arm®

Day 1

Introduction to the Arm Architecture

Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions 

Arm Tools Overview

Arm DS-5 • Tool Licensing • GNU and ABI • Debug Interfaces 

Assembler Programming for Arm Processors

Load/Store Instructions • Data Processing Instructions • Flow Control • Miscellaneous • DSP 

Day 2

 

Exception Handling

Exceptions overview • Interrupts sources and priorities • Abort Handlers • SVC Handlers • Undef Handlers • Reset Handlers 

Arm Caches and TCMs

Cache basics • Caches on Arm processors • Tightly Coupled Memory (TCM) • Optimization consideration 

Using the MPU

Memory Management Introduction • Access Permissions and Types • Memory Protection Unit (MPU) • Optimizations & Issues 

Synchronization

Atomicity • LDREX/STREX Uses • Mutex Implementation 

Barriers

Data barriers • Instruction barriers 

Day 3

 

Software Engineers' Guide to the Cortex-R4

Introduction • L1 memory system 

Power Management for Cortex-A/R Cores

Processor Power Consumption • Power Modes • NEON and MPCore 

C/C++ Compiler Hints & Tips

Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data issues 

Linker & Libraries Hints & Tips

Linking Basics • System and User Libraries • Veneers and Interworking • Linker Optimizations and Diagnostics • Arm Supplied Libraries 

Day 4

 

Further Compiler/Linker Hints & Tips

Mixing C/C++ and Assembler • Stack Issues • VFP/NEON • Advanced Building Facilities 

Embedded Software Development

An "Out-of-the-box" build • Tailoring the C library to your target • Tailoring image memory map to your target • Reset and Initialization • Further memory map considerations • Building and debugging your image 

Debug and Profiling

Invasive Debug • Non-Invasive Debug • PMU • Trace 

Appendix

 

GIC Programming

Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions

The learning is reinforced with unique Lab exercises using the QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life. Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on a combination of GNU compilation tools, GDB and an instruction set simulator used for fast prototyping. Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/DDD and QEMU).