• Design engineers who wish to make full use of SystemVerilog's class-based verification capabilities for test bench development as well as learning SystemVerilog for RTL design.
• Verification engineers aiming to deploy coverage driven verification approaches for the first time using SystemVerilog
• Verification engineers wishing to migrate to SystemVerilog class-based verification from other established verification languages and test bench automation techniques
• Engineers and managers who wish to evaluate the full range of SystemVerilog's capabilities for design and verification
• EDA support engineers who wish to gain a comprehensive understanding of how their customers' engineering teams can most productively use SystemVerilog in both design and verification domains

The course is structured into distinct sections.

• SystemVerilog for Design and Verification (days 1-3) which includes:
  
  
  • SystemVerilog Basics (¾ day) lays the foundation for learning the SystemVerilog language for design and for verification.
    
    
  • SystemVerilog RTL (½ day) teaches the synthesizable RTL language features of SystemVerilog. For hardware designers, this assumes an understanding of RTL synthesis with Verilog or VHDL. For verification engineers, this provides some familiarity with the RTL constructs as used by hardware designers.
    
    
  • SystemVerilog Assertions (¾ day) teaches the principles of assertion-based design and verification and the features of the SystemVerilog Assertion language.
    
    
  • Module-based SystemVerilog Verification (1 day) teaches the verification features of SystemVerilog that can be used in module-based code. It also provides a foundation for class-based verification.
• Class-based SystemVerilog Verification (days 4-5) describes how to write sophisticated constrained-random, coverage-driven, object-oriented testbenches. This material leverages Doulos's years of experience in teaching object-oriented verification concepts, making these challenging topics accessible to engineers with a wide variety of backgrounds. This course has been specifically tailored to provide the ideal preparation for learning UVM or a similar verification methodology.

Comprehensive SystemVerilog provides the essential SystemVerilog language foundations for learning the Universal Verification Methodology. Doulos also offers follow-on training in this. For further details, see UVM Adopter Class.

A good working knowledge of Verilog is essential:

• For engineers with no HDL knowledge or experience the Doulos Comprehensive Verilog course, or equivalent, is an essential precursor.
• For engineers with no Verilog knowledge, but with working experience of VHDL, Doulos offer a Fast Track Verilog for VHDL Users class in a format tailored to equip delegates with the necessary foundation for SystemVerilog.
• For onsite courses, precursor training in Verilog can be tailored to the specific team profile and combined with appropriate SystemVerilog modules to fully address team needs (see Modular SystemVerilog).

If you require any of these precursor training options please contact the Doulos team to discuss what will best suit your needs, or complete an online enquiry.

Doulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:

• Fully indexed class notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• Doulos SystemVerilog Golden Reference Guide e-book for language, syntax, semantics and tips

If you would prefer a paperback version of your Doulos Golden Reference Guide, this can be purchased from the Doulos online shop.

SystemVerilog for Design and Verification (days 1-3)

SystemVerilog Basics

Introduction

What is SystemVerilog? • Language Evolution • SystemVerilog Language Features • Caveats • The UVM Family Tree • Books and Resources

Verilog versus SystemVerilog

Logic Type • Reg, Logic, and Bit • Nets versus Variables - Refresh • Wire versus Var

Programming Language Features

C-Like Language Features • Static vs Automatic Variables • Static vs Automatic Tasks • ++, --, and Assignment Operators • Labeling • Time Units • Do While Loop • Immediate Assertions • join_none and join_any • Enhanced Tasks and Functions • Task and Function Arguments • Void Functions • Argument and Return Types • Type string • $sformat and $sformatf

Bus-Functional Modeling

Simple Module-Based BFM • Testbench using BFM • Separate Test from Test Harness

Basic Data Types

4-state and 2-state Types • Initial Values • Caveats with Signed Types • Enumerations • Type-Checking of Enumerations • struct • typedef struct • Packed Struct • Packed and Unpacked Arrays • Indexing Multidimensional Arrays • Packages • Packages and Ports

Interfaces

Simple Interface • Package versus Interface • Instantiating an Interface • Accessing Interface Members • Ports and Parameters on Interfaces • Pin-Level Interface • Modports • Generic Interface Ports • Task/Function in Interface • Calling Task through Interface Port

SystemVerilog RTL

RTL Processes

SystemVerilog and RTL Synthesis • Combinational Logic • Clocked Processes • always_comb, always_latch, always_ff • Synthesis-Friendly If / Case • priority case • unique if • unique case • Wild Equality Operators • case inside • inside Operator

RTL Types

Synthesizable Data Types • Enums for Finite State Machines • Base Types and Values • Rules for Overriding the Enum Values • Packed Struct (Review) • Packed Union • Multidimensional Arrays • Nets, Ports and Data Types • Types and Packages • Type Parameters • Synthesis of Interfaces • Multiple Drivers on a Bus • How to Differentiate Connections? • Modport Expressions • Modport Expressions with Generate

SystemVerilog Assertions

The SVA Language

What are Properties? • Property versus Assertion • Benefits Of Assertions • Who Writes Properties? • Immediate and Concurrent Assertions • Immediate Assertions • Assertion Failure Severity • Concurrent Assertions • Temporal Behaviour • Clocks and Default Clocks • Holds and Implication • Non-overlapped Implication • Simulation of Assertions • Assertion Coverage • Simulation and Cover Property • Binding

Properties, Assertions and Sequences

Implication • Properties are checked on every clock • |=> and |-> • $rose() and $fell() • $rose() vs posedge • $past() • $sampled() • Properties using Expressions • Named Properties • Sequences – Basic Syntax • Concatenation • Repetition • Consecutive Repetition • Unbounded Repetitions • Zero Repetitions • Non-Consecutive and Goto Repetition • Sequence versus Implication • $rose() and $fell() versus Sequence

More on Properties & Sequences (Optional Topic)

Sequence Operators • Sequence Or • Sequence and • Non-Length-Matching and • Sequence Length-Matching and • Throughout • Within • first_match • Property Operators • Beware Negating Implications • Operator Precedence • Named Sequences and Properties • Sequence Completion • Variables and Procedures in Sequences • Detecting the Endpoint of a Sequence • Turning Assertions Off

Module-based SystemVerilog Verification

Clocking Blocks

Clocking Block Syntax • Input and Output Skew • Creating a Clocking Block • Testbench and Clocking Block • Cycle Delays and Clocking • Input and Output Skew Syntax Summary • Scheduler Regions • Stimulus and Response • Signal Aliasing • Multiple Clocking Blocks • Driving a Net • Clocking Blocks in Interfaces • Clocking Blocks versus Programs

Randomization

Constrained Random Verification • Random Numbers in SystemVerilog • std::randomize • Constraint Syntax • Seeding and Random Stability • Saving & Restoring Seeds • Random Sequence of Valid Actions • Randcase • Randsequence

Coverage

Functional Coverage • Coverage Bins • Further Options • Transition Coverage • Cross Coverage • Adjusting Stimulus Using Coverage

Arrays and Queues

Dynamic Arrays • Queues • Working with Queues • Queue Methods • Nesting, Assignment Patterns, and %p • Array-like Containers • Associative Arrays • Associative Array Methods • Foreach

Other Language Features (Optional Topic)

$root and $unit • Enumeration Methods • Arrays for Multidimensional Structures • Initializing an Unpacked Array • Replication in an Assignment Pattern • Packed Arrays and Structures • Pass-by-Copy • Pass-by-Reference • const ref • Array Querying Functions • $bits • Bit-stream Casting • Array Manipulation Methods • Array Locator Methods • Array Ordering Methods • Array Reduction Methods • Other IEEE 1800-2009 Features

The Direct Programming Interface (Optional Topic)

DPI Simulation Flow • Command-line Switches • Importing a C Function • Changing the Imported Function Name • Mapping Data Types of Arguments • Exporting a Function to C • Sandwiches and Transparency • Importing and Exporting Tasks • Scalar Bit and Logic Arguments • Packed Arrays • Decoding the Canonical Representation • String Arguments • Open Array Arguments • Task Return Values • Task Disable Flow • Pure and Context

Class-based SystemVerilog Verification (days 4-5)

Classes for Transactions

Constrained Random Verification • Representing Transaction Data • SystemVerilog Classes • Object = Instance of Class • Constructor • Constructor Arguments

Class Members and Copying

Static Data Members • Constant Data Members • Randomized Data Members • Data Members of Class Type • Forward Typedef • Object Copy with new • Shallow Copy • Deep or Shallow Copy?

Virtual Interfaces

Test Harness and Testbench • Modules versus Classes • Creating the Testbench • Virtual Interface • Building a test harness • Adding a clocking block • Connecting the virtual interface • Accessing a Task through a Modport • Testbench Static Structure • BFM or Driver Class • Testbench Object Structure

Extending Classes for Stimulus

Improved Generator Class • Constrained randomization • Creating an Extended Class • The Inheritance Relationship • Inheriting Class Members • Control Knobs and Constraints • Methods of Extended Class • Derived-class Object, Base-class Variable • Virtual Methods • General-Purpose Infrastructure

TLM and Channels

Reusable Verification Environments • Transaction Level Modeling • Using Channels • Generic Channel and Transaction Classes • Out-of-Block Declarations • Connecting Channels • Getting Data from a Generic Channel • Safe Downcasting with $cast • Type Parameterization of Classes • Running Components with fork...join • fork...join_none • Identifying Forked Processes

Component Hierarchy

Testbench Component Hierarchy • Implementing Relationships • Base Classes (review) • Abstract Class and Pure Virtual Methods • Interface Classes in IEEE 1800-2012 • Component Base Class • Launching a Task with fork...join_none • Customising a Component • Constructing a Component

Monitors and Checkers

Kinds of BFM-Like Component • Monitors and Checkers • Bus Protocol Checking • Modports for Driver and Monitor • Monitor Implementation • Using the Monitored Transactions • Checker Implementation • Mutual Exclusion • Semaphore Class • Checker with Mutual Exclusion

Functional Coverage

Coverage Driven Verification • Verification Planning • From Features to Tests • Covergroups • Embedded Covergroups • Procedural Sampling • Arguments and Options • Coverage Bins • Bins and Coverage • Cross Coverage • Cross Coverage and Labels • Cross Coverage Example • Controlling Cross Bins

More on Constraints (Optional Topic)

Inline Constraints • Overriding Constraints • Procedural Control of Randomization • Procedural Control of Constraints • Constraint Ordering • Function Calls within a Constraint • Constraining Dynamic Arrays • Constraining an Array-of-Objects • Arrays within a Constraint • Hierarchical Constraints • unique • Soft Constraints

Processes and Events (Optional Topic)

The std Package • What is a “processâ€? • fork...join_none • fork...join_any • wait fork • disable fork • Identifying Processes • Fine-grain Process Control • Process Control Example • Mailbox Class • Using Mailboxes • Enhanced Events