Thanks for taking the time to visit Doulos at this year's conference
This page has brought together a range of Doulos courses and FREE webinars and tutorials for you. Enjoy!
If you would like to explore training options with Doulos, check out the listing below and then contact your local Doulos team directly, or complete a webform*.
IP, FPGA and SoC Design and Verification Courses
Self-Paced Training
Upcoming KnowHow Webinars
The primary goal in safely implementing any IC or FPGA project is to achieve a synchronous design. This implies that the relationship of all clocks and asynchronous resets to each other is defined in the synthesis constraints. Incorrect handling of clock-domain crossing (CDC) is probably the primary cause of sporadic errors, which are impossible to catch in a digital simulation and can cause a system to inexplicably fail in the field.
This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.
Topics include:
- What causes metastability
- How to correctly implement CDC logic for simple signals, complex data and counters
- How to use Synopsys Design Constraints (SDC) to ensure that static timing analysis (STA) produces reliable results in the context of multi-clock designs
The webinar will also feature a working example from Microchip Technology using PolarFire® FPGAs and SoCs and the Libero® SoC Design Suite.
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In this webinar Doulos Senior Member of Technical Staff, David C Black, will introduce the key concepts of randomization and constraints in SystemVerilog.
As well as the principles of Constrained Random Verification, you will be provided with an overview of the language constructs to support this, the generation of data and methods for constraining the data.
You will also learn about numerous randomization features and the many approaches for configuration and control.
All the examples are supported by working code that you can run on Doulos' free simulation environment EDA Playground using the Questa Advanced Simulator from our webinar partner Siemens.
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Check out the latest live webinar schedule »
KnowHow Webinars On-Demand and Tutorials
Is formal verification ready for general use or do you need a PhD to use it? Larger companies continue to recruit formal PhDs into their verification teams while other less-well-qualified engineers seem reluctant to go beyond simplified formal "apps".
So, what is the truth of the matter? Can non-specialist engineers become productive with formal?
In this webinar Doulos Co-Founder and Technical Fellow, John Aynsley will explore the strengths and weaknesses of formal verification.
Using the VC Formal™ tool from Synopsys® as an example, John will explain exactly what you need to know to use formal effectively without acquiring deep knowledge of how it works under-the-hood.
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Formal verification is known to work well in areas like control logic, interface protocols, and so on, but it is often dismissed for use on data paths since capacity becomes a significant issue. In particular, packet based protocols have potentially very large state spaces, which can pose a problem for formal. However, in this paper, a step by step process is presented, showing how to decompose a frame of data into simple formal constraints, modeling code, and assertions, which allows formal to fully explore the entire packet state space.
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An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. That is where helper code comes to the rescue. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis. Likewise, formal analysis may need to reduce the complexity of the problem and state space, which helper code can also help. So where are some places to use helper code and when?
This article looks at how helper code can be used to simplify our properties, model formal abstractions, constrain formal inputs, and aid formal analysis.
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In this paper, eight common asynchronous scenarios are presented and SVA solutions for checking them. In addition, an alternative approach using a global fast clock is presented as both a portable simulation solution and something that works for both formal verification and emulation. Lastly, incorporating functional coverage into the asynchronous checking is also discussed.
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This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.
Doulos CTI Brian Jensen, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using QuestaSim from Siemens-EDA in the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.
Topics include:
- Wire vs Variable Assignments
- Static vs Automatic Variables
- Static vs Automatic Tasks
- Assignments in Tasks – Pass-by-Copy
- Assignments in Tasks – Pass-by
- Reference
- Enumerations
- struct and packed struct
- Equality Operators
- Equality between vectors
- SVA Temporal Behavior
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Learning any new programming language will undoubtedly be influenced by your existing design experience, and although that knowledge is largely very useful it can also work against you... For example, when you come to learn VHDL, the parallel nature of the hardware design language might trip you up if you've been using a language that has a sequential nature, such as Java, C or C++.
In this webinar VHDL guru, Doug Perry, (author of "VHDL: Programming by Example") explores some of the common mistakes designers make when starting out with VHDL and provides useful tips and resources for getting on track. Practical examples will be provided using Aldec Riviera-PRO™ in the online simulation environment EDA Playground.
Content Summary:
- VHDL Statements
- Process Statements
- Signal Assignments
- Delta Delays
- The Simulation Cycle
- Variables
- Incomplete Assignments
- Unexpected Latches
- Drivers
- Types
- Expressions
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SystemC has become well-established as the language of choice for system modeling and virtual platform creation and integration, and is now being applied successfully for high level synthesis. SystemC models also frequently appear as reference models in the hardware verification flow.
This session is aimed at hands-on hardware or software engineers who might know Verilog or C but have no previous experience of SystemC. It will explain what you need to know to be successful with SystemC by exploring some fundamental questions including:
- What is SystemC and how is it used?
- What does modern SystemC code look like?
- What differentiates SystemC from SystemVerilog?
- What use cases best fit SystemC?
- What is TLM?
- Where can I learn more?
The session will be presented by David C Black, Doulos Senior Member of Technical Staff and co-author of "SystemC: From the Ground Up". It will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.
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View all on-demand webinars available »
About Doulos Training
For over 30 years, Doulos has been dedicated to developing the skills, capability and productivity of engineers designing the latest technologies.
The essential choice for independent training to over 5,400 companies spanning 84 countries, Doulos provides scheduled classes and bespoke team training both In-Person and Live Online. The course portfolio includes hardware design and verification languages and methodologies, embedded software, AI and deep learning.
Our business ethos is 'Service through Excellence' which, when combined with our industry-leading KnowHow™, makes Doulos the ideal training partner.
Contact Doulos now »
