Global training solutions for engineers creating the world's electronics

Welcome attendees of the DVCon US 2024

Thanks for taking the time to visit Doulos at this year's conference

This page has brought together a range of Doulos courses and FREE webinars and tutorials for you. Enjoy! 

If you would like to explore training options with Doulos, check out the listing below and then contact your local Doulos team directly, or complete a webform*. 

DVCon US 2024 Paper by Senior Member Technical Staff, Doug Smith:

Practical Asynchronous SystemVerilog Assertions

This paper and associated code is now available to download here.

View the presentation details on the DVCon website here.

KnowHow Webinars On-Demand and Tutorials

This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.

Doulos CTI Brian Jensen, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using QuestaSim from Siemens-EDA in the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.

Topics include:

  • Wire vs Variable Assignments
  • Static vs Automatic Variables
  • Static vs Automatic Tasks
  • Assignments in Tasks – Pass-by-Copy
  • Assignments in Tasks – Pass-by
  • Reference
  • Enumerations
  • struct and packed struct
  • Equality Operators
  • Equality between vectors
  • SVA Temporal Behavior

 

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Doulos Co-Founder & Technical Fellow John Aynsley teaches the core principles necessary to understand and use SystemVerilog Assertions, focussing on the aspects of SVA that are applicable to both formal verification and simulation.

Particular emphasis is on the core semantics of temporal logic so that you will be able to write your own assertions, understand what you are doing, and avoid the many pitfalls that trap beginners.

SVA is really not hard if you approach it properly!

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Formal verification is known to work well in areas like control logic, interface protocols, and so on, but it is often dismissed for use on data paths since capacity becomes a significant issue. In particular, packet based protocols have potentially very large state spaces, which can pose a problem for formal. However, in this paper, a step by step process is presented, showing how to decompose a frame of data into simple formal constraints, modeling code, and assertions, which allows formal to fully explore the entire packet state space.

VIEW THIS TUTORIAL ON THE DOULOS WEBSITE NOW »

An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. That is where helper code comes to the rescue. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis. Likewise, formal analysis may need to reduce the complexity of the problem and state space, which helper code can also help. So where are some places to use helper code and when?

This article looks at how helper code can be used to simplify our properties, model formal abstractions, constrain formal inputs, and aid formal analysis.

VIEW THIS ARTICLE ON THE DOULOS WEBSITE NOW »

VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary.

This webinar seeks to answer the questions you may not have had answered in the past; shedding light on the mystery of VHDL configurations and showing a practical example of how to apply them, using Synopsys VCS in the Doulos EDA Playground environment.

Topics include:

  • VHDL Entity and Architecture
  • Direct Instantiation
  • Component Declaration and Instantiation
  • VHDL Configuration Declaration
  • Default Binding Rules
  • Hierarchical and Nested Configurations
  • Other Capabilities
  • Compilation Order and Configurations

 

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This webinar explores debugging SystemC code with basic tools, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without getting lost and obtaining information about SystemC simulation status. The session concludes with ideas on how to simplify debugging and accelerate development.

The webinar is suitable for SystemC programmers of any level. It will cover:

  • SystemC debug challenges
  • Tools
  • Demo:
    • Configuring the code
    • .gdbinit
  • Strategies & Wrap-up

The webinar also features the Virtualizer Studio IDE from Synopsysfor browsing, editing and debug of SystemC source code.

The webinar is presented by David C Black, Doulos Senior Member of Technical Staff and co-author of "SystemC: From the Ground Up".

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SoC Design and Verification Courses

About Doulos Training

For over 30 years, Doulos has been dedicated to developing the skills, capability and productivity of engineers designing the latest technologies.

The essential choice for independent training to over 5,400 companies spanning 84 countries, Doulos provides scheduled classes and bespoke team training both In-Person and Live Online. The course portfolio includes hardware design and verification languages and methodologies, embedded software, AI and deep learning.

Our business ethos is 'Service through Excellence' which, when combined with our industry-leading KnowHow™, makes Doulos the ideal training partner.

Contact Doulos now »

Looking for team-based training, or other locations?

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