Global training solutions for engineers creating the world's electronics products

Clock Domain Crossing

Friday June 24 2022

1 hour session (All Time Zones)

Asia and Europe

Friday, June 24, 2022

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)


Americas

Friday, June 24, 2022

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)


The primary goal in safely implementing any IC or FPGA project is to achieve a synchronous design. This implies that the relationship of all clocks and asynchronous resets to each other is defined in the synthesis constraints. Incorrect handling of clock-domain crossing (CDC) is probably the primary cause of sporadic errors, which are impossible to catch in a digital simulation and can cause a system to inexplicably fail in the field.

This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.

Topics include:

  • What causes metastability
  • How to correctly implement CDC logic for simple signals, complex data and counters
  • How to use Synopsys Design Constraints (SDC) to ensure that static timing analysis (STA) produces reliable results in the context of multi-clock designs

The webinar will also feature a working example from Microchip® using PolarFire® FPGAs and SoCs and the Libero® SoC Design Suite.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com


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Hardware Design training available from Doulos:

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