Global training solutions for engineers creating the world's electronics

FPGA & ASIC Design Using VHDL

VHDL is a hardware description language used to describe the structure and behaviour of digital electronic hardware designs, such as FPGAs and ASICs. VHDL is an abbreviation of VHSIC (very high speed integrated circuit) Hardware Description Language.



Doulos training credentials

Doulos has set the industry standard for VHDL training since it delivered one of the world's first VHDL training classes in 1991. Since then, nearly 1000 company sites across the world have chosen Doulos' FPGA and ASIC VHDL design expertise to get their engineers project-ready, enhance their design skills and improve productivity.

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  • Train using the tools of your choice
    Because Doulos is an independent company, you benefit from learning VHDL using the EDA tools of your choice. And because we aren't aligned to any particular vendor, you'll learn coding styles that maximise the portability of code between EDA tools, rather than approaches tuned to a particular tool. (Unless of course we're delivering in-house training, in which case the training is tailored to your specific design context). Tools supported by these courses include:

    • Aldec Active HDL™ & Riviera-PRO™
    • Cadence Incisive®
    • Mentor Graphics ModelSim® & Questa®
    • Synopsys VCS®
    • Synopsys Synplify Pro®
    • Synopsys Design Compiler®
    • Mentor Graphics Precision® RTL
  • Get the best project reference material
    We've all been on a training class that squeezes too much detail on to a slide, jumps around the subject, and supplies class notes that you can't easily reference after the class.....Doulos training materials are not like that! Tutor's notes accompany the slides, an index makes them an excellent project reference, and our famous VHDL Golden Reference Guide has 198 pages packed with syntax, hints, tips and practical advice. Doulos training materials really are sought after references in their own right.

  • Learn faster and more easily
    Doulos tutors make learning easier, faster, and enjoyable! Experienced design engineers themselves, they combine a talent for teaching with indepth understanding and experience of real world design issues and solutions. And, drawing on nearly 20 years of Doulos' corporate training experience, our tutors really know what it takes to create and deliver effective training.

  • Customize in-house training to match your requirements
    Doulos excels at tailoring in-house training to meet your exact training needs - including tool and technology focus. You'll find us very easy to work with - flexible, professional and with a guarantee of the expert technical interaction you need to ensure you get the best for your team, and the most from your budget.

Training programs for FPGA & ASIC designers

  • Essential Digital Design Techniques
    Essential Digital Design Techniques provides the ideal first stage in full scale project training for graduate design engineers, or engineers moving into digital design from other disciplines (including software or analog design). As such, it is the natural precursor to the Doulos Comprehensive VHDL class. With a strong emphasis on practical design and hands-on workshops, this class has been developed to significantly cut the on-the-job learning curve by capturing design techniques usually learned over months, in an intensive 2-day class.
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  • Learning PathComprehensive VHDL (5 days)
    Comprehensive VHDL has been the industry's gold standard VHDL training class since 1991. It is quite simply the fastest, most effective way to get project-ready. You'll gain the expertise you need to write efficient, re-usable RTL code, and create test benches powerful enough to cope with complex designs.

    Comprehensive VHDL comprises 2 modules:

    • VHDL for Designers (days 1-3)
      Provides a solid foundation for Altera designers, especially those needing to apply the more advanced features of VHDL covered in the Advanced VHDL module. Covers the FPGA design flow with practical, hands-on exercises throughout, and delegates leave with a flexible project infra-structure to use, adapt and extend on projects after the class. Workshops include dedicated labs illustrating the use of Quartus II in the FPGA tool flow.
    • Advanced VHDL (days 4-5)
      Pre-requisite training for engineers targeting large FPGAs, such as Stratix® IV. Focuses on testbenches to cope with more complex designs, and design for re-use.

    View the learning path for Comprehensive VHDL »
    View the full Comprehensive VHDL course description and dates »

  • Learning PathExpert VHDL (5 days)
    Expert VHDL has become essential training for engineers working on large or complex designs. Without it, efficiency and productivity can suffer, causing time-to-market and development costs to increase.

    Expert VHDL is presented in two modules.

    • Expert VHDL Design (days 1-2) teaches you to write better, more efficient code that is easier to maintain and re-use.
    • Expert VHDL Verification (days 3-5) shows you how to speed up and improve design verification; make testbench writing easier and more effective for even the most complex testbenches, and create behavioural models to make tests run faster.

    View the learning path for this Expert VHDL »

    View the full Expert VHDL course description and dates »

  • Essential Perl
    Perl is a widely-used cross-platform programming language, which is especially valuable to engineers targeting ASICs and and large FPGAs. Perl's process, file, and text manipulation facilities, in particular, enable skilled users to achieve a range of productivity boosting short-cuts, and avoid easy-to-make mistakes that are time consuming to fix. Essential Perl, unlike other Perl classes, is focused on the needs of EDA users. It covers the essential subset of the Perl5 scripting language and is packed with design related exercises and examples including: patching netlists, filtering reports, generating test vectors, and running tools.
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  • Essential Tcl/Tk
    Tcl/Tk is a powerful way to manage your design process, automate otherwise error-prone and time-consuming tasks and achieve valuable gains in efficiency and productivity. Every VHDL user and EDA support specialist needs to know about Tcl. Unlike the numerous Tcl text books and classes available, the Doulos Essential Tcl/Tk class is focused on the needs of EDA users, and it's packed full of examples and exercises directly based on design related problems.
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  • FPGA Professional Designer Program™
    The FPGA Professional Designer Program addresses critical design needs for engineers tackling designs using Altera or Xilinx devices and tools. Altera Professional Designer™ and Xilinx Professional Designer™ programmes provide the best combination of HDL, design flow and techncial training modules.

  • RapidGain™ training events
    Doulos RapidGain™ training events deliver unique opportunities to obtain a combination of hands-on experience and know-how at a fraction of the cost and duration of full scope training classes. There are currently 4 classes in the hardware design portfolio:
    RapidGain™ VHDL using Altera
    RapidGain™ VHDL using Lattice
    RapidGain™ VHDL using Xilinx
    RapidGain™ - Optimizing Performance for Altera

Client Support

Doulos Project Services is a powerful resource giving your company rapid access to expertise for direct use on project issues. A wide range of packages exist to assist you through all stages of methodology and language decision making, integration and design use. All our packages can be provided with the flexibility to provide support exactly when required, maximising the benefit to cost ratio.
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