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When to use Helper Code to Accelerate Formal Analysis

1 hour session (All Time Zones)
Presenter: Doug Smith

Senior Member Technical Staff

Asia and Europe

Time: 10-11am (BST) 11am-12pm (CEST) 2.30-3.30pm (IST)


Time: 10-11am (PDT) 11am-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

Webinar Overview:

Although a formal verification environment can be quickly created with a few simple properties that immediately start finding design issues, it's not easy to model all design behaviors using SystemVerilog's property syntax. This results in complex or numerous properties, or behaviors, that require more than just SVA.

That is where "helper code" comes to the rescue.

In this webinar for formal verification users, we look at when and where helper code can be used effectively to describe properties, model formal abstractions, constrain formal inputs, and control and aid formal analysis. Our goal is to help you accelerate your formal analysis.

Topics include:

• What is helper code?
• Why SVA isn’t always enough
• How helper code aids property development
• How helper code aids formal analysis

The webinar features code running in Siemens Questa™ Formal Apps - however the principles will be useful to anyone with a working understanding of formal verification.

Doug Smith

Doug Smith - Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Attendance is free of charge

If you have any queries, please contact

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