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Arm Cortex-A9 for Intel SoC FPGA
A mixed class covering both the system and software aspects of designing with a Arm® Cortex®-A9 MPCore based device. This class highlights the Cortex-A9 MPCore architecture details and the Intel® SoC FPGA implementation choices. Including topics such as the Arm exceptions' model, details of the available caching schemes and coherency management, memory management and the Arm memory model as well as the AMBA AXI bus protocol. Additionally the Arm assembly section delivers the essential knowledge required for programming and debugging an Arm v7 based application processor.
Laboratory exercises are provided to reinforce the acquired knowledge and comprise approximately 25% of the class.
Delegates should have some knowledge of embedded systems, and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.
A carefully crafted combination of content from Arm, Intel and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes:
Intel SoC FPGA architecure overview
Introduction to Arm assembler programming
Caches
Exception Handlers for Arm application processors
Memory Management
Using the NEON co-processor
Writing C for Arm Processors
Synchronization
Embedded software development
Software Engineers' Guide to Intel SoC FPGA
MPCore Logic
TrustZone
Appendix:
The AMBA AXI bus protocol
Linker and Libraries Hints and Tips
Exercises:
Exercises can be provided for both the Arm and GNU tool chain.
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