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Arm Cortex-A9 for Intel SoC FPGA

Formerly Altera SoC FPGAs

Standard Level - 3 days

A mixed class covering both the system and software aspects of designing with a Arm® Cortex®-A9 MPCore based device. This class highlights the Cortex-A9 MPCore architecture details and the Intel® SoC FPGA implementation choices. Including topics such as the Arm exceptions' model, details of the available caching schemes and coherency management, memory management and the Arm memory model as well as the AMBA AXI bus protocol. Additionally the Arm assembly section delivers the essential knowledge required for programming and debugging an Arm v7 based application processor.

Laboratory exercises are provided to reinforce the acquired knowledge and comprise approximately 25% of the class.

  • Engineers who wish to become skilled in the use of a Cortex-A9 based System On Chip from a software development and verification perspective
  • Engineers who need to understand integration details centered around the AXI protocol
  • Engineers who will required to provide a software solution to bring a bare metal Cortex-A9 MPCore system to life
  • The hardware structure of an Intel SoC FPGA
  • The details of a Cortex-A9 processor core
  • The details of the MPCore logic
  • Memory management for Arm v7 based devices
  • AXI system interfaces
  • The required software skills needed to bring up a bare metal system

Delegates should have some knowledge of embedded systems, and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.

A carefully crafted combination of content from Arm, Intel and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.

Training material includes:

  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples to help you apply your knowledge.

Intel SoC FPGA architecure overview

  • Architecture details with Cortex-A9 MPCore implementation choices
  • Core and FPGA interfaces
  • Hard Processor System Built-in peripherals
  • Memories and memory controllers
  • FPGA logic and rooting details
  • I/O peripherals
  • Processor system boot options
  • Development and debugging software
  • Cortex-A9 core building blocks
  • Private peripherals
  • Snoop control unit
  • Accelerator coherency Port (ACP)
  • Generic interrupt controller
  • Core system interfaces

Introduction to Arm assembler programming

  • Load/Store Instructions
  • Data Processing Instructions
  • Data Processing Instructions
  • Flow Control
  • Miscellaneous
  • DSP


  • Cache basics
  • L1 and L2 Caches on Arm based SoCs
  • Caches' configuration options
  • Optimization considerations

Exception Handlers for Arm application processors

  • Exceptions overview
  • Interrupts sources and priorities
  • Abort handlers
  • SVC handlers
  • Undef handlers
  • Reset handlers

Memory Management

  • Memory Management Introduction
  • Access Permissions and Types
  • Memory Management Unit (MMU)
  • Optimizations & Issues

Using the NEON co-processor

  • NEON instruction set overview
  • NEON software support

Writing C for Arm Processors

  • Parameter passing
  • Floating point linkage
  • Alignment
  • Coding considerations


  • Synchronization overview
  • Synchronization primitives
  • LDREX STREX applications

Embedded software development

  • An out-of-the-box” build
  • Tailoring the C library to your target
  • Tailoring image memory map to your target
  • Reset and initialization
  • Further memory map considerations
  • Building and debugging your image

Software Engineers' Guide to Intel SoC FPGA

  • Overview
  • Interconnect and interfaces
  • Level 1 memory system
  • Branch prediction

MPCore Logic

  • MPCore Features
  • Snoop Control Unit
  • Accelerator Coherency Port (ACP)
  • Interrupt Controller
  • Timer and watchdog
  • TrustZone Support
  • Developing for Arm MPCore Processors
  • Booting SMP
  • Configuring an interrupt
  • Synchronization


  • Exception handling
  • Memory system
  • Debug
  • Software


The AMBA AXI bus protocol

  • Protocol overview
  • Channels, transfers & transactions
  • Channel signal
  • Transfer behavior
  • Transaction ordering
  • AXI terminology

Linker and Libraries Hints and Tips

  • Linking basics
  • System and user libraries
  • Veneers and interworking
  • Linker optimizations and diagnostics
  • Arm Supplied Libraries


  • DS-5/GNU toolchain introduction tutorial
    Cover the use of command line and GUI tools to build and debug projects.
  • Assembler programming for Arm
    Practice with the concepts covered in the Arm assembly module.
  • Exception handler programming
    Study a complete system with vector table, exception handlers stubs and stacks setup

Exercises can be provided for both the Arm and GNU tool chain.

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